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And-inverter graph
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#	Item
11	Microsoft Word - haig14.doc Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2008-05-20 20:12:25 Digital electronics Electronic design And-inverter graph Retiming Logic optimization Automatic test pattern generation Combinational logic Formal verification Logic programming Electronic engineering Formal methods Electronic design automation
12	Speculative Reduction-Based Scalable Redundancy Identification Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2009-05-13 19:49:55 Applied mathematics Theoretical computer science Logic Electronic design automation Mathematical induction Proof theory Mathematical proof Formal verification And-inverter graph Mathematics Mathematical logic Formal methods
13	Improvements to Technology Mapping for LUT-Based FPGAs Alan Mishchenko Satrajit Chatterjee Robert Brayton Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2006-02-27 22:53:37 Diagrams And-inverter graph Logic synthesis Field-programmable gate array Directed acyclic graph Algorithm Heuristic function Electronic engineering Electronic design automation Electrical engineering
14	DAG-Aware AIG Rewriting A Fresh Look at Combinational Logic Synthesis Alan Mishchenko Satrajit Chatterjee Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2006-05-08 11:02:22 Digital electronics Electronic design Logic in computer science And-inverter graph Logic synthesis Field-programmable gate array American International Group Directed acyclic graph Logic gate Electronic engineering Electronic design automation Formal methods
15	Microsoft Word - fpga061s-mishchenko1.doc Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2009-12-16 19:04:56 Digital electronics Electronic design And-inverter graph Field-programmable gate array Logic synthesis Static timing analysis Placement Logic optimization Propagation delay Electronic engineering Electronic design automation Formal methods
16	Improvements to Combinational Equivalence Checking Alan Mishchenko Satrajit Chatterjee Robert Brayton Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2006-08-09 21:17:37 Formal methods Logic in computer science NP-complete problems And-inverter graph Diagrams Boolean satisfiability problem Satisfiability Logic synthesis Automatic test pattern generation Electronic engineering Theoretical computer science Electronic design automation
17	Cut-Based Inductive Invariant Computation Michael Case1,2 1 Alan Mishchenko1 Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2008-04-28 18:02:46 Formal methods Logic in computer science Electronic design automation Mathematical logic Programming paradigms And-inverter graph Logic programming Model checking Boolean satisfiability problem Theoretical computer science Mathematics Applied mathematics
18	Applying Logic Synthesis for Speeding Up SAT Niklas Een, Alan Mishchenko, Niklas S¨ orensson Cadence Berkeley Labs, Berkeley, USA. EECS Department, University of California, Berkeley, USA. Chalmers University of Technol Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2007-03-20 02:33:25 Theoretical computer science Conjunctive normal form And-inverter graph Science Mathematics Circuit Canonical form Boolean network Logic Electronic design automation Formal methods
19	Microsoft Word - imfs27.doc Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2008-12-20 12:21:03 Formal methods Mathematics Logic Boolean algebra Diagrams And-inverter graph Boolean satisfiability problem Canonical form Lookup table Theoretical computer science Computing Electronic design automation
20	SAT-Based Logic Optimization and Resynthesis Alan Mishchenko Robert Brayton Jie-Hong Roland Jiang Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2007-04-23 22:32:02 Electronic design automation Boolean network Science Mathematics Design Diagrams Formal methods And-inverter graph